This application claims the benefit of Korean Patent Application No. 2001-6179, filed on Feb. 8, 2001, under 35 U.S.C. xc2xa7 119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a signal line arrangement method thereof
2. Description of the Related Art
As semiconductor memory devices become highly highly integrated, efficient layout of the memory cells is required. A conventional semiconductor memory device includes a plurality of memory cell array blocks, a plurality of local data input/output line pairs connected to a plurality of the memory cell array blocks, multiple column selecting signal lines and a plurality of global data input/output line pairs arranged in the orthogonal direction with the plurality of local data input/output line pairs. As shown in FIG. 1, the column select signal lines CSL1, CSL2, . . . , CSLn and the plurality of global data input/output line pairs (GIO1 and GIO1B) and (GIO2 and GIO2B) are arranged in the same direction and are located adjacent to each other in the memory cell array. Typically each of the column select signal lines delivers a full swing signal, and the pair of global data input/output lines delivers smaller swing signals. A problem associated with such signal layout is the conflicting of the column select signal to the adjacent global data input/output lines due to coupling capacitance.
For example, the semiconductor memory device of FIG. 1 includes memory cell array blocks such as BL1, BL2, BL3, and BL4, pairs of local data input/output lines such as (LIO1 and LIO1B), (LIO12 and LIO12B), (LIO23 and LIO23B), (LIO34 and LIO34B), and (LIO4 and LIO4B), a word line WL, column selecting signal lines CSL1, CSL2, . . . , CSLn, and pairs of global data input/output lines such as (GIO1 and GIO1B) and (GIO2 and GIO2B). The word line WL is arranged along the direction of the pairs of local data input/output lines LIO1 and LIO1B. The column select signal lines CSL1, CSL2, . . . , CSLn and pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2, and GIO2B) are arranged in a direction orthogonal to the pairs of local data input/output lines LIO1 and LIO1B. Column selecting signal lines CSL1, CSL2, . . . , CSLn are arranged adjacent to pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B).
Referring to FIG. 2, which is a schematic diagram illustrating coupling capacitances between a column selecting signal line and global data input/output line pair in the conventional semiconductor memory device. The column selecting signal line CSL1 and the global data input/output line pair GIO1 and GIO1B are divided in three parts, and CA1, CB1, CC1, and CD1 are coupling capacitances in the memory cell array block BL1, BL2, BL3, and BL4, respectively, between the column selecting signal line CSL1 and the global data input/output line GIO1. CA2, CB2, CC2, and CD2 are coupling capacitances in the memory cell array block BL1, BL2, BL3, and BL4, respectively, between the global data input/output line pair GIO1 and GIO1B. CA3, CB3, CC3, and CD3 are coupling capacitances in the memory cell array block BL1, BL2, BL3, and BL4, respectively, between the column selecting signal line CSL1 and the inverting global data input/output line GIO1B.
When the column selecting signal line CSL1 is enabled or disabled, the sum of coupling capacitances, CA1+CB1+CC1+CD1, couples the signal of the CSL1 line and affects a signal in the global data input/output line GIO1. If the coupling is severe, the signal of the global data input/output line GIO1 can change according to the signal change of the column selecting signal line CSL1.
In the same way, when the column selecting signal line CSL1 is enabled and/or disabled, the signal of the inverting global data input/output line GIO1B can change according to the signal change of the column selecting signal line CSL1. However, the inverting global data input/output line GIO1B is located farther than the global data input/output line GIO1 from the column selecting signal line CSL1, the effect of CSL1 on the inverting global data input/output line GIO1B is less than the signal of the global data input/output line GIO1.
Referring to FIG. 3, which is an operation-timing diagram of the memory cell array block BL1 of FIG. 1, and more particularly illustrating a case that an inverting write enable signal WEB of xe2x80x9chighxe2x80x9d logic level is applied and data of xe2x80x9clowxe2x80x9d logic level is read from pairs of bit lines BLP1 and BLP2.
A row address X is inputted in response to a row address strobe signal RASB of xe2x80x9clowxe2x80x9d logic level, and a column address Y is inputted in response to a column address strobe signal CASB of xe2x80x9clowxe2x80x9d logic level. By decoding the row address X, a word line enable signal WL of xe2x80x9chighxe2x80x9d logic level is generated, and also block selecting signals BLS 1 and BLS 12 of xe2x80x9chighxe2x80x9d logic level are generated. By decoding the column address Y, a control signal of xe2x80x9chighxe2x80x9d logic level in the column selecting signal line CSL1 is generated. In addition, the precharge signal PRE of xe2x80x9clowxe2x80x9d logic level is generated before the word line enable signal WL of xe2x80x9chighxe2x80x9d logic level is generated. In response to the precharge signal PRE of xe2x80x9clowxe2x80x9d logic level, pairs of bit lines BLP1 and BLP2, pairs of local data input/output lines LIO1, LIO1B, LIO2, and LIO2B, and pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B) are precharged.
When the word line enable signal WL of xe2x80x9chighxe2x80x9d logic level starts to generate, each pair of bit lines BLP1 and BLP2 begins to develop toward xe2x80x9chighxe2x80x9d logic level and xe2x80x9clowxe2x80x9d logic level, respectively.
When the control signal of xe2x80x9chighxe2x80x9d logic level in the column selecting signal line CSL1 of is generated, data of pairs of bit lines BLP1 and BLP2 are transmitted to pairs of local data input/output lines (LIO1 and LIO1B) and (LIO12 and LIO12B). In response to block selecting signals BLS1 and BLS2, data in pairs of local data input/output lines (LIO1 and LIO1B) and (LIO12 and LIO12B) are transmitted to corresponding pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B), and are amplified by input/output sense amplifiers.
When data in each pair of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B) start to develop toward xe2x80x9chighxe2x80x9d logic level and xe2x80x9clowxe2x80x9d logic level, the input/output sense amplifiers detect a voltage difference of the data transmitted to pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B), and then amplify the voltage difference. Therefore, the faster the starting time developing toward xe2x80x9chighxe2x80x9d logic level and xe2x80x9clowxe2x80x9d logic level in data transmission to pairs of global data input/output lines (GIO1 and GIO1B) and (GIO2 and GIO2B), the faster the data read access time.
However, the conventional semiconductor memory device arranges the column selecting signal line CSL1 and the global data input/output line GIO1 adjacently as shown in FIG. 2. Therefore, the coupling capacitances between the column selecting signal line CSL1 and the global data input/output line GIO1 affect data transmitting to a pair of global data input/output lines GIO1 and GIO1B. In other words, a full swing to xe2x80x9chighxe2x80x9d logic level in the column selecting signal line CSL1 increases a voltage of a xcex94V1 level in the global data input/output line GIO1. A transition to xe2x80x9clowxe2x80x9d logic level in the column selecting signal line CSL1 lowers a voltage of a xcex94V1 level in the global data input/output line GIO1. On the other hand, the voltage of the inverting global data input/output line GIO1B is increased slightly.
In other words, when a signal in the column selecting signal line CSL1 is enabled and disabled, data of global data input/output line GIO1 is affected changed due to a large coupling capacitance between the column selecting signal line CSL1 and the global data input/output line GIO1. Therefore, the starting point of valid data appearance of the pair of global data input/output lines GIO1 and GIO1B is delayed around xcex94T1, thereby delaying a read data access time.
To overcome the above described problems, preferred embodiments of the present invention provide a semiconductor memory device reducing a coupling capacitance between a column selecting signal line and a pair of a global data input/output line so that a read data access time can be improved.
To achieve the above object, the semiconductor memory device of the present invention comprises a plurality of memory cell array blocks, a certain numbers of pairs of local data input/output lines in a plurality of the memory cell array blocks, multiple column selecting signal lines arranged in the orthogonal direction of pairs of local data input/output lines, and a number of pairs of global data input/output lines that a pair of global data input/output lines twists at least more than once to be arranged adjacently in the same direction with the column selecting signal line.
According to an alternative preferred embodiment of the present invention, the semiconductor memory device of the present invention provides a method of signal line arrangement comprising a plurality of memory cell array blocks, a certain numbers of pairs of local data input/output lines in a plurality of the memory cell array blocks, multiple column selecting signal lines arranged in the orthogonal direction of pairs of local data input/output lines, and a certain numbers of pairs of global data input/output lines that a pair of global data input/output lines twists at least more than once to be adjacently in the same direction with the column selecting signal line.